A comparative evaluation of algorithms for converting numbers and hardware implementation of combinational code converters are considered. Universal algorithms for converting numbers from one positional number system to another are presented, which are essential for the hardware implementation of converters that perform the translation. The offered comparative evaluation of the algorithms transfer binary integers in BCD and BCD to binary proper fractions. It showed that common feature of these algorithms is the composition of arithmetic operations. Generation in the FPGA of Boolean functions of many variables by tabulated converters allows to reduce the number of stages and code converters and along with other high-performance parameters to achieve low latency propagation (~35-50 ns) and low power consumption.