The binary algorithms translation analysis of proper fractions in binary-coded decimal and binary-coded decimal integers in binary code was held. It was revealed that the rational choice of algorithms of both types of translation was required to perform the same arithmetic operations, all actions must be performed on the binary-decimal numbers in the decimal system. To implement the converters considered codes and numbers are appropriate hardware BCD 8421. At the same time for both types of transfers required to perform the same correction tetrads elementary transducers of the same type. It is shown that the combination of the elementary transducers reduces the number of stages of the combinational circuit multi-bit converters. Simulation of 32-bit binary code converter proper fractions in binary-coded decimal, the scheme is implemented on the FPGA SPARTAN-II, SPARTAN-3, SPARTAN-6 firm Xilinx, showed that the propagation delay is about 35...50 ns.